Project Brief and Partners

DICECUP is joint research project in the area of random number generation in FPGAs. The ultimate goal is to provide a software application that generates VHDL or VERILOG code to implement true random number generators with respect to the employed FPGA family and the requirements of the user.

DICECUP is carried out by the following project partners:
University of Technology Dresden
Chair for Embedded Systems
Siemens AG
Corporate Technology
secunet Security Networks AG
Bereich Hochsicherheit

General Information